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6.4 Shared Memory
6.1 Node Model 6.2 ASM Model 6.3 Lock Constructs 6.4 Shared Memory 6.5 Distr. Memory 6.6 VPP Systems 6.7 OS View 

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6.4 Shared Memory Systems

To explain the idea of TRIs and TSIs better, the examples of implementing stress-flow with three different type of node interconnections will be discussed.


FIG. 34: Implementation of stress-flow on common shared memory systems

FIG. 34 shows implementation of stress-flow on systems with common shared memory. This includes “Symmetrical Multi-Processing” systems with single memory accessed by many processors through shared bus as well as systems with processor-memory interconnecting crossbars or similar such circuits, the key characteristics of such a system being the fact that all memory can be accessed by different processors equally well, translating to no need to group preferred tasks for different processing nodes. Organization of TRIs and TSIs in this situation reflects the physical characteristics of the system and its inherent “centralization.” The parameter location information is either non-existent or empty here. TRIs and TSIs are here not separate components but simply different fronts for the same common centralized component as shown on FIG. 34.  This centralized component consists of two FIFO queues: FIFO of Ready Tasks and FIFO of Free Nodes (Processors). Ready tasks incoming to separate TSIs are all placed in the same FIFO of Ready Tasks (tasks ready to be executed). The top (oldest) task in this FIFO is matched with any node/processor that becomes available (i.e. is placed in the FIFO of Free Nodes). Such matched pair becomes the specific node TRI’s incoming task that begins to execute. When a task ends, the processor is returned to the TRI, which places it back in the FIFO of Free Nodes. Such functionality means that when one of these FIFOs is non-empty, the other one is empty (it may have only one element for a very brief moment).

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First published 03/29/06. Last modified: 06/25/10