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5.3 Microprocessors
5.1 Stack Use 5.2 Internals 5.3 Microprocessors 5.4 Parallel HW 5.5 VPP HW 

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5.3 Implementation in Microprocessors

To be able to implement the rudimentary synchronization mechanisms and to be able to safely share common memory in multi-processor architecture, prior art depended on special “interlocked memory” microprocessor instructions and that guaranteed that only one processor could perform such “interlocked memory” instructions on the same data at the same time. Stress-flow can and actually was implemented in multi-processor hardware using such instructions. 

The key feature of stress-flow is that all process synchronization and shared data protection is performed solely by means operations on the lock variable associated with every stress-flow atom. Therefore, multiprocessor hardware design can be greatly simplified by implementing stress-flow as part of microprocessor core. Simply providing a special purpose register to store the address of the currently used lock variable would not only eliminate need for all interlocked memory access instructions completely, it would also allow performing all synchronization and process control by means of single instruction. Just as currently produced microprocessors have program counter or stack pointer special registers, the proposed microprocessor would have a “lock address register.”

All microprocessor operations with the lock register null are the same as before. Otherwise, the operations look like this: Attempt to assign an address to the lock register (microprocessor move instruction with lock register as destination) attempts to reserve the lock. Subroutine call instruction with lock register set initiates execution on another thread or processor. Return instruction with lock register set marks the lock for release and zeroes the lock register.

This way all of stress-flow functionality is accomplished by means of one special-purpose register and single microprocessor instructions related to it.  “Move” instruction involving the lock register would be the only operations requiring memory interlocking shared memory – a great simplification in designing symmetrical parallelism capable microprocessors.

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First published 03/29/06. Last modified: 06/25/10